(1) Field of the Invention
The invention relates to a method to manufacture an integrated circuit device, and, more particularly, to a method to form a floating gate for a split-gate flash memory in the manufacture of an integrated circuit device.
(2) Description of the Prior Art
Non-volatile memory devices are widely used in the art of electronics. Non-volatile memories provide stored data to an electronic system in a form that can be retained even during a loss of system power. Non-volatile memory can take the form of one-time programmable devices, such as electrically programmable read-only memory (EPROM), or re-programmable devices, such as electrically erasable, programmable read-only memory (EEPROM). A particular type of EEPROM that is of interest in the present invention is the flash EEPROM. A flash EEPROM provides a means to rapidly erase the EEPROM memory array prior to programming or re-programming.
Referring now to FIG. 6, exemplary flash EEPROM devices 10 are shown in cross sectional representation. A flash device is a MOSFET device where a complex gate is used. The complex gate comprises a floating gate 22a and a control gate 42. The floating gate 22a comprises a first conductor layer 22a overlying the substrate 14 with a gate dielectric layer 18 therebetween. The control gate comprises a second conductor layer 42 in close proximity to the floating gate 22a and with a second dielectric layer 38 lying between the first and second conductor layer 22a and 42. Further, the example devices are split-gate devices. In a split-gate device, the channel region of the substrate 14—the region of the substrate 14 between the drain region 58 and the common source region 62—is controlled by two distinct gate regions. In a first area, the floating gate 22a directly overlies the channel region. In a second area, the control gate 42 directly overlies the channel region.
In the flash device, the memory transistor is turned ON—such that current can conduct from drain 58 to source 62—when the control gate 42 bias is large enough to invert the entire channel region. Note that in the second region, where the control gate directly overlies the channel, the control gate can directly control the channel. However, in the first region, where the floating gate directly overlies the channel region, the biasing action of the control gate is mitigated by the intervening floating gate. As a result, a voltage bias on the control gate is divided across the series capacitance of the floating gate prior to interacting with the channel.
The flash device exhibits two, distinct states: programmed and erased. In the erased state, the floating gate 22a, is devoid of excess electron charge. In the programmed state, the floating gate 22a has a large amount of excess electron charge trapped on the first conductor layer 22a. The presence of excess electron charge on the floating gate increases the effective threshold voltage (Vth) of the device. That is, a larger gate voltage must be applied to the control gate to turn on the flash device in the programmed (excess electron) state than in the erased state (no excess electrons) state. In the applied circuit, a current sensing mechanism is used to determine the ON-OFF state of the device in the presence of a standard control voltage and a drain-to-source voltage. The determined ON-OFF state is used to “read” the stored data state of the cell as a “0” or a “1”. Alternatively, in a multiple-state device, any of several threshold voltages Vth may by stored by trapping various, relative amounts of charge on the floating gate 22a. 
Programming and erasing of the flash device are accomplished by forcing the control gate 42, drain 58, and source 62 to voltages beyond the ranges used during reading or standby operations. For example, to program the flash device, a positive voltage is forced onto the control gate 42, or word line, of the cell, while the drain 58 is biased to a relatively large voltage and the source 62 is grounded. As a result, electrons will flow from drain to source. However, the high energy of the electrons, due to the large drain 58 bias, will cause some of the electrons to tunnel through the thin, first dielectric 18 and to enter the floating gate electrode 22a. These electrons are then trapped in the floating gate 22a once the programming bias is removed. To erase the device, a large positive voltage is forced on the control gate 42 while the drain 58 and source 62 are grounded. The trapped electrons can tunnel across the second dielectric layer 38 to the control gate 42 and discharge the floating gate 22a. 
It is desirable in the art to structure the flash device in such a way as to achieve rapid programming and erasing times while exhibiting very stable and long enduring data retention. The exemplary flash device exhibits two techniques that are used in the art to provide these characteristics. First, the split-gate structure offers a significant advantage over a structure, called a stacked gate, where the control gate 42 directly overlies the floating gate 22a but not the channel. By forming a part of the control gate 42 directly over the channel region of the substrate 14, the split-gate device provides significantly better performance during an over-erase event. In an over-erase event, the floating gate 22a is discharged beyond a neutral condition. As a result, the floating gate 22a actually contains too little electron charge and this causes the Vth of the device to fall. If the floating gate 22a is over-erased far enough, then device will become a depletion device where the channel is effectively ON all of the time even in the absence of a positive voltage on the control gate 42. In a stacked gate device, an over-erase condition will cause excessive leakage current that can limit the operating performance of the cell and of the overall array. The split-gate form reduces the over-erase effect because the Vth of the device in the channel region directly underlying the control gate 42 is not affected by the over-erase condition. Therefore, the control gate 42 will hold the channel OFF during the standby state and eliminate the leakage current even if the floating gate is over-erased.
A second feature of the exemplary device 10 is the use of lateral floating gate tips 24. Floating gate tips 24 cause a concentration of the electric field between the control gate 42 and the floating gate 22a during an erasing operation. As a result, the floating gate 22a can be erased more completely and more quickly than in a comparable flash device that does not have these tips 24. In this way, the erasing conditions, and especially the control gate voltage, can be made less severe and hazardous to the long-term reliability of the device.
Referring now to FIGS. 1 through 6, an exemplary method of forming lateral, floating gate tips 24 is illustrated. Referring in particular to FIG. 1, the device 10 is again shown in a partially completed, cross sectional representation. A first dielectric layer 18, such as silicon oxide, is formed overlying the substrate 14. A first conductor layer 22, such as polysilicon, is then formed overlying the first dielectric layer 18. A masking layer 26, such as silicon nitride, is formed overlying the first conductor layer 22. The masking layer 26 is then patterned to expose the first conductor layer 22 where the floating gates are planned 30.
Referring now to FIG. 2, the first conductor layer 22 is oxidized to grow a thick layer of thermal oxide 34 overlying and consuming part of the first conductor layer 22. This process is called a local oxidation of silicon, or LOCOS, oxidation and is similar to the approach traditionally used to form field oxide regions. The thermal oxide layer 34 exhibits a well-known shape where the oxide is tapered at the edges of the masking layer 26. Referring now to FIG. 3, the masking layer 26 is then removed. In FIG. 4, the first conductor layer 22 is etched through, using the LOCOS oxide layer 34 as a mask, to form the floating gate electrodes 22a. Note how the tapered cross-section of the LOCOS oxide layer 34 creates the lateral tips 24 on the first conductor layer 22a of each floating gate. Referring now to FIG. 5, the second dielectric layer 38 and second conductor layer 42 are formed to create the control gates 42 for each cell. Referring again to FIG. 6, subsequent process steps may include forming the source 62 and drain 58 regions by ion implantation, forming sidewall spacers 54, forming silicide 46 to reduce gate resistivity, and capping 50 the complex gates.
The above-described method of formation results in a useful, split-gate device having a vertically tipped, floating gate. However, it is found that the LOCOS oxide hard mask 34 creates a difficult to control floating gate etch process. As a result of poor process control, some devices exhibit a “weak erase” condition where the floating gate is not adequately erased by the standard erase procedure. Achieving an improved method to form a tipped floating gate, split-gate flash device is therefore a desirable outcome of the present invention.
Several prior art inventions relate to flash memory devices and methods of manufacture. U.S. Pat. No. 6,570,790 B1 to Harari describes several EPROM and flash EEPROM devices showing alternative floating gate shapes. Lateral tips on floating gates are shown. U.S. Pat. No. 6,531,734 B1 to Wu discloses a split-gate flash memory device and method of manufacture. U.S. Pat. No. 6,171,906 B1 to Hsieh et al discloses a split-gate flash device and method of manufacture showing a floating gate with an erasing tip formed using LOCOS. U.S. Pat. No. 6,165,845 to Hsieh et al describes a split-gate flash device and method of manufacture. An angled etch is used to create an angled floating gate prior to using LOCOS to form the floating gate tips.